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features ? fast read access time ? 150 ns automatic page write operation ? internal address and data latches for 64 bytes ? internal control timer fast write cycle times ? page write cycle time: 3 ms or 10 ms maximum ? 1 to 64-byte page write operation low power dissipation ? 50 ma active current ? 200 a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology ? endurance: 10 4 or 10 5 cycles ? data retention: 10 years single 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout full military and industrial temperature ranges green (pb/halide-free) packaging option 1. description the ft 28c256 is a high-performance electrically erasable and programmable read- only memory. its 256k of memory is organized as 32,768 words by 8 bits. manufac- tured with force's advanced nonvolatile cmos technology, the device offers access times to 150 ns with power dissipation of just 440 mw. when the device is deselected, the cmos standby current is less than 200 a. the ft 28c256 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. during a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a writ e cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. force's ft 28c256 has additional features to ensure high quality and manufacturabil- ity. the device utilizes internal error co rrection for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inadvertent wr ites. the device also includes an extra 64 bytes of eeprom for device identification or tracking. 256k (32k x 8) paged parallel eeprom ft28c256 1/22
2. pin configurations pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect 2.1 28-lead pga top view 2.2 32-pad lcc, 28-l ead plcc top view note: plcc package pins 1 and 17 are don?t connect. 2.3 28-lead cerdip/pdip/flatpack/ top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd dc i/o3 i/o4 i/o5 a7 a12 a14 dc vcc we a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 256k (32k x 8) paged parallel eeprom ft28c256 2/22
3. block diagram 4. device operation 4.1 read the ft 28c256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexib ility in preventing bus cont ention in their system. 4.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latc hed on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has been started it will automati- cally time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effect ively be a polling operation. 4.3 page write the page write operation of the ft 28c256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded the ft 28c256 will cease accept ing data and commence the internal program- ming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a6 - a14 inputs. for each we high to low transition during the page write operation, a6 - a14 must be the same. the a0 to a5 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be wr itten; unnecessar y cycling of other bytes within the page does not occur. 4.4 data polling the ft 28c256 features data polling to indicate the end of a wr ite cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at an ytime during the write cycle. 256k (32k x 8) paged parallel eeprom ft28c256 3/22
4.5 toggle bit in addition to data polling the ft 28c256 provides another method for determin ing the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop tog- gling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. 4.6 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. force has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 hardware protection hardware features protect against inadvertent writes to the ft 28c256 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay ? once v cc has reached 3.8v the device will automatica lly time out 5 ms (typical) before allowing a write; (c) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 4.6.2 software data protection a software controlled data protection feature has been implemented on the ft28c256. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the ft 28c256 is shipped from force with sdp disabled. sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addr esses (refer to ?software data protection? algo- rithm). after writing the 3-byte command sequence and after t wc the entire ft 28c256 will be protected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the ft 28c2 56. this is done by pr eceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp will remain active unless the disable command sequence is issued. power transi- tions do not disable sdp and sd p will protect the ft 28c256 duri ng power-up and power-down conditions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without th e 3-byte command sequence will start the internal write timers. no data will be wr itten to the device; however, for the duration of t wc , read operations will effe ctively be polling operations. 4.7 device identification an extra 64 bytes of eeprom memory are available to the user for device identification. by rais- ing a9 to 12v 0.5v and using address locations 7fc0h to 7fffh the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 optional chip erase mode the entire device can be erased using a 6-byte software code. please see ?software chip erase? application note for details. 256k (32k x 8) paged parallel eeprom ft28c256 4/22
notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 5. dc and ac operating range ft 28c256-15 ft 28c256-20 ft 28c256-25 ft 28c256-35 operating temperature (case) ind. -40c - 85c mil. -55c - 125c -55c - 125c -55c - 125c -55c - 125c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% 6. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 7. absolute maximum ratings* temperature under bias ............. .............. ..... -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground .............. .....................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground .............. .....................-0.6v to +13.5v 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v ind. 200 a mil. 300 a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 3 ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -400 a 2.4 v 256k (32k x 8) paged parallel eeprom ft28c256 5/22
10. ac read waveform s (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter ft 28c256-15 ft 28c256-20 ft 28c256-25 ft 28c256-35 units min max min max min max min max t acc address to output delay 150 200 250 350 ns t ce (1) ce to output delay 150 200 250 350 ns t oe (2) oe to output delay 0 70 0 80 0 100 0 100 ns t df (3)(4) ce o r oe to output float 0 50 0 55 0 60 0 70 ns t oh output hold from oe , ce or address, whichever occurred first 0000 n s 256k (32k x 8) paged parallel eeprom ft28c256 6/22
11. input test waveforms and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns 13 . pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46p fv in = 0v c out 81 2p fv out = 0v 256k (32k x 8) paged parallel eeprom ft28c256 7/22
note: 1. nr = no restriction 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 50 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )1 0 0n s t ds data setup time 50 ns t dh , t oeh data, oe hold time 0 ns t dv time to data valid nr (1) 256k (32k x 8) paged parallel eeprom ft28c256 8/22
17. page mode write waveforms (1)(2) notes: 1. a6 through a14 must specify the same page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 18. chip erase waveforms 16. page mode characteristics symbol parameter min max units t wc write cycle time (option available) ft 28c256 10 ms ft 28c256f 3 ms t as address setup time 0 ns t ah address hold time 50 ns t ds data setup time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns t s = t h = 5 sec (min.) t w = 10 msec (min.) v h = 12.0v 0.5v 256k (32k x 8) paged parallel eeprom ft28c256 9/22
19. software data protection enable algori thm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) 20. software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3) 21. software protected write cycle waveforms (1)(2) notes: 1. a6 through a14 must specify the same p age address during each high to low transition of we (or ce ) after the software code has been entered. 2. oe must be high only when we and ce are both low. 256k (32k x 8) paged parallel eeprom ft28c256 10/22
notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 6 . 23. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. s ee ?ac read characteristics? on page 6 . 25. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 22. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output del ay (2) ns t wr write recovery time 0 ns 24. toggle bit charac teristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns 256k (32k x 8) paged parallel eeprom ft28c256 11/22
26. normalized i cc graphs 256k (32k x 8) paged parallel eeprom ft28c256 12/22
27. ordering in formation (2) 27.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 150 50 0.2 ft 28c256(e,f)-15ji ft 28c256(e,f)-15pi ft 28c256(e,f)-15si ft 28c256(e,f)-15ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 0.3 ft 28c256(e,f)-15dmb ft 28c256(e,f)-15fmb ft 28c256(e,f)-15lm b ft 28c256(e,f)-15umb 28d6 28f 32l f 28u class b, fully compliant (-55 c to 125 c) 200 50 0.3 ft 28c256(e,f)-20dm b ft 28c256(e,f)-20fm b ft 28c256(e,f)-20lm b ft 28c256(e,f)-20um b 28d6 28f 32l f 28u class b, fully compliant (-55 c to 125 c) 250 50 0.3 ft 28c256(e,f)-25dm b ft 28c256(e,f)-25fm b ft 28c256(e,f)-25lmb ft 28c256(e,f)-25umb ft 28c256(e,f)-35um b 28d6 28f 32l f 28u 28u class b, fully compliant (-55 c to 125 c) package type 28d6 28-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 28f 28-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32j 32-lead, plastic j-leaded chip carrier (plcc) 32l f 32-pad, non-windowed, ceramic leadless chip carrier (lcc) 28p6 28-lead, 0.600" wide, plastic dual inline package (pdip) 28u 28-pin, ceramic pin grid array (pga) w die options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles f fast write option: write time = 3 ms 256k (32k x 8) paged parallel eeprom ft28c256 mil - std- 883bm5004 mil - std- 883bm5004 mil - std- 883bm5004 13/22
27.2 green package option (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 150 50 0.2 ft 28c256(f)-15ju ft 28c256(f)-15pu ft 28c256(f)-15su ft 28c256(f)-15tu 32j 28p6 28s 28t industrial (-40 c to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28p6 28-lead, 0.600" wide, plastic dual inline package (pdip) options blank standard device: endurance = 10k write cycles; write time = 10 ms f fast write option: write time = 3 ms 256k (32k x 8) paged parallel eeprom ft28c256 14/22
28. valid part numbers the following table lists standard and green force products that can be ordered. device numbers speed package and temperature combinations ft 28c256 15 ji, ju, pi, pu, si, su, ti, tu, dm b , fmb , lmb , umb ft 28c256e 15 ji, pi, si, ti, dm b , fm b, lmb , umb ft 28c256f 15 ji, ju, pi, pu, si, su, ti, tu, dm b , fmb , lmb , umb ft 28c256 20 dm b , fm b , lm b , umb ft 28c256e 20 dm b , fm b , lm b , umb ft 28c256f 20 dmb , fm b , lm b , umb ft 28c256 25 dm b , fm b , lm b , umb ft 28c256e 25 dm b , fm b , lm b , umb ft 28c256f 25 dm b , fm b , lm b , umb 29. die products reference section: parallel eeprom die products 256k (32k x 8) paged parallel eeprom ft28c256 15/22
packaging information 29.1 28d6 ? cerdip title r 28d6, 28-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 37.85(1.490) 36.58(1.440) pin 1 15.49(0.610) 12.95(0.510) 0.127(0.005)min 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 17.80(0.700) max 0.46(0.018) 0.20(0.008) 2.54(0.100)bsc 5.08(0.200) 3.18(0.125) seating plane 5.72(0.225) max 33.02(1.300) ref 0o~ 15o ref dimensions in millimeters and (inches). controlling dimension: inches. mil- std - 883bm5004 (glass sealed) 256k (32k x 8) paged parallel eeprom ft28c256 16/22
29.2 28f ? flatpack title r 28f, 28-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) dimensions in millimeters and (inches). controlling dimension: inches. mil - std - 883bm5004 pin #1 id 9.40(0.370) 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) bsc 1.14(0.045) max 3.02(0.119) 2.29(0.090) 1.14(0.045) 0.660(0.026) 7.26(0.286) 6.96(0.274) 1.96(0.077) 1.09(0.043) 0.23(0.009) 0.10(0.004) 10.57(0.416) 9.75(0.384) 18.49(0.728) 18.08(0.712) 256k (32k x 8) paged parallel eeprom ft28c256 17/22
29.3 32j ? plcc r title 32j, 32-lead, plastic j-leaded chip carrier (plcc) 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ 256k (32k x 8) paged parallel eeprom ft28c256 18/22
29.4 32l ? lcc title 32lf, 32-pad, non-windowed, ceramic lid, leadless chip carrier (lcc) dimensions in millimeters and (inches). controlling dimension: inches. mil-std - 883bm5004 11.63(0.458) 11.23(0.442) 14.22(0.560) 13.72(0.540) 2.54(0.100) 2.16(0.085) 1.91(0.075) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45? 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45? pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 7.62(0.300) bsc 1.27(0.050) typ 10.16(0.400) bsc 256k (32k x 8) paged parallel eeprom ft28c256 19/22
29.5 28p6 ? pdip title 28p6, 28-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 36.703 ? 37.338 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ab. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010"). 256k (32k x 8) paged parallel eeprom ft28c256 20/22
29.8 28u ? pga title r 28u, 28-pin, ceramic pin grid array (pga) dimensions in millimeters and (inches). controlling dimension: inches. 13.74(0.540) 13.36(0.526) 15.24(0.600) 14.88(0.586) 2.57(0.101) 2.06(0.081) 7.26(0.286) 6.50(0.256) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 12.70(0.500) typ 2.54(0.100) typ 16.71(0.658) 16.31(0.642) 2.54(0.100) typ 10.41(0.410) 9.91(0.390) 256k (32k x 8) paged parallel eeprom ft28c256 21/22
ashley crt, henley, marlborough, wilts, sn8 3rh uk tel: +44(0)1264 731200 fax:+44(0)1264 731444 e-mail info@forcetechnologies.co.uk tech@forcetechnologies.co.uk sales@forcetechnologies.co.uk www.forcetechnologies.co.uk life support applications force technologies products are not designed for use in life support appliances, devices or systems where malfunction of a force technologies product can reasonably be expected to result in a personal injury. force technologies customers using or selling force technologies products for use in such applications do so at their own risk and agree to fully indemnify force technologies for any damages resulting from such improper use or sale. products, and makes no representation or warranties that that these products are free from patent, copyright or mask work infringement, unless all trademarks acknowledged copyright force technologies ltd 200 7 unless otherwise stated in this scd/data sheet, force technologies ltd reserve the right to make changes, without notice, in the products, includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. force technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. 22/22

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